What is the von Noyman structure?
The von Neumann structure, also known as the Princeton structure, is a memory structure that combines program instruction memory and data memory. The program instruction storage address and the data storage address point to different physical locations in the same memory, so the width of the program instructions and data are the same. For example, the program instructions and data of Intel's 8086 central processor are both 16 bits wide.
Structure introduction:
Speaking of the development of computers, we cannot but mention the American scientist von Neumann. Since the early 20th century, physics and electronics scientists have debated what structure should be used to build machines that could perform numerical calculations. People are troubled by the decimal system, the counting method that humans are accustomed to. Therefore, the call for the development of analog computers was louder and more powerful at that time. In the mid-1930s, American scientist von Neumann boldly proposed that he abandon the decimal system and use binary as the basis of the number system for digital computers. At the same time, he also said that calculation programs are pre-programmed, and then the computer performs numerical calculations according to the calculation sequence set by people in advance.
People call this theory of von Neumann the von Neumann architecture. From EDVAC to the most advanced computers today, all use the von Neumann architecture. Therefore, von Neumann is the undisputed father of digital computers.
Electronic computer systems designed using this concept and principle are collectively referred to as "Von Norman structure" computers. Von Norman architecture processors use the same memory and transmit via the same bus.
Content
Features Von Neumann structure processor has the following characteristics:
1: There must be a memory;
2: There must be a controller;
3: There must be an arithmetic unit to complete arithmetic operations and logical operations;
4: There must be input devices and output devices, Used for human-machine communication.
: In addition, programs and data are stored uniformly and work automatically under program control
Function
A computer based on the von Neumann architecture must It has the following functions:
Send the required programs and data to the computer.
Must have the ability to long-term memory programs, data, intermediate results and final calculation results.
The ability to complete various arithmetic, logical operations and data transmission and other data processing capabilities.
Able to output processing results to users as required.
In order to complete the above functions, the computer must have five basic components,
including:
Input devices for inputting data and programs;
Memory that stores programs and data;
Arithmetic unit that completes data processing;
Controller that controls program execution;
Outputs processing results output device.
Bottleneck
? Separating the CPU and memory is not perfect, but will lead to the so-called von Neumann bottleneck: the flow between the CPU and memory ( Data transfer rate) is quite small compared to the capacity of the memory. In modern computers, the traffic is very small compared to the efficiency of the CPU. In some cases (when the CPU needs to execute some simple instructions on huge data time), data flow becomes a very serious limitation on overall efficiency. The CPU will be idle while data is being input or output to memory. Since the growth rate of CPU speed and memory capacity is much greater than the traffic between the two parties, the bottleneck problem is becoming more and more serious. The von Neumann bottleneck was the first time John Backus appeared in his 1977 ACM Turing Award acceptance speech. According to Backus:
"...there is indeed a change storage device The method is more advanced than circulating a large amount of data through the von Neumann bottleneck. The term bottleneck is not only a description of the data flow of the problem itself, but more importantly, it is also a way of limiting our thinking to 'one character at a time'. Patterns of intelligence bottlenecks. It discourages us from thinking about broader concepts. So programming becomes a matter of planning and specifying the flow of character data through the von Neumann bottleneck, and most of the problem is not the characteristics of the data, but How to find data."
Cache memory between the CPU and memory solves the von Neumann bottleneck performance problem. In addition, the establishment of branch prediction (branch predictor) algorithms also helps alleviate this problem. The "intelligence bottleneck" discussed by Backus in 1977 has changed a lot. And Backus had no discernible impact on the solution to this problem. Modern functional programming and object-oriented programming have rarely performed "operations of moving large numbers of values in and out of memory" like early Fortran, but to be fair, these operations do take up most of the computer's execution time.
The architecture of the central processing unit can be divided into: von Neumann structure and Harvard structure
Central processors and microcontrollers using the von Neumann structure are a lot of.
In addition to Intel's 8086 mentioned above, Intel's other central processors, ARM's ARM7, and MIPS' MIPS processors also use the von Neumann structure.
In 1945, von Neumann first proposed the concept of "stored program" and the binary principle. Later, electronic computer systems designed using this concept and principle were collectively referred to as "Von Neumann". Mann-type structure" computer. Von Neumann architecture processors use the same memory and are transmitted via the same bus.
The Von Norman structure processor has the following characteristics: it must have a memory; it must have a controller; it must have an arithmetic unit to complete arithmetic operations and logical operations; it must have input and Output device used for human-computer communication.
Harvard structure
? Harvard structure is a memory structure that separates program instruction storage and data storage. The central processing unit first reads the program instruction content from the program instruction memory, decodes it to obtain the data address, then reads the data from the corresponding data memory, and performs the next operation (usually execution). The separation of program instruction storage and data storage allows instructions and data to have different data widths. For example, the program instructions of Microchip's PIC16 chip are 14-bit wide, while the data is 8-bit wide.
Harvard structure microprocessors usually have higher execution efficiency. Its program instructions and data instructions are organized and stored separately, and the next instruction can be read in advance during execution. There are many central processors and microcontrollers that use Harvard architecture. In addition to Microchip's PIC series chips mentioned above, there are also Motorola's MC68 series, Zilog's Z8 series, ATMEL's AVR series and ARM's ARM9 , ARM10 and ARM11.
The Harvard architecture refers to an architecture in which program and data spaces are independent, with the purpose of alleviating the memory access bottleneck when the program is running.
For example, in the most common convolution operation, one instruction fetches two operands at the same time. During pipeline processing, there is also an instruction fetch operation. If the program and data are accessed through a bus, the instruction fetch and Fetching numbers will inevitably cause conflicts, which is very detrimental to the execution efficiency of loops with large operations. The Harvard structure can basically solve the conflict between index fetching and number fetching. To access another operand, you can only use the Enhanced Harvard structure. For example, like TI, the data area is split and an additional bus is added. Or like AD, use instruction cache, and the instruction area can store part of the data.
In the DSP algorithm, one of the largest tasks is to exchange information with the memory, which includes sample data, filter coefficients and program instructions as input signals. For example, if you multiply 2 numbers stored in memory, you need to take 3 binary numbers from memory, namely 2 numbers to be multiplied and 1 program instruction describing how to do it. DSP generally adopts Harvard structure internally, which has at least 4 sets of buses in the chip: program data bus, program address bus, data data bus and data address bus. This separate program bus and data bus allows simultaneous acquisition of instruction words (from program memory) and operands (from data memory) without interfering with each other. This means that instructions and operands can be prepared simultaneously in one machine cycle. Some DSP chips also contain other buses, such as DMA buses, etc., which can complete more work in a single cycle. This multi-bus structure is like setting up a highway extending in all directions inside the DSP, ensuring that the computing unit can obtain the required data in a timely manner and improving the computing speed. Therefore, for DSP, the internal bus is a resource. The more buses there are, the more complex functions can be completed. SuperHarvard architecture (superHarvard architecture, abbreviated as SHARC), which adds an instruction cache (cache) and a dedicated I/O controller to the Harvard architecture.
The Harvard architecture processor has two obvious characteristics: it uses two independent memory modules to store instructions and data respectively. Each memory module does not allow instructions and data to coexist; it uses two independent buses. , respectively, as a dedicated communication path between the CPU and each memory, and there is no connection between the two buses.
? The improved Harvard structure has the following structural characteristics: to achieve parallel processing; it has an independent address bus and an independent data bus, and uses a common address bus to access two storage modules (program storage module and Data storage module), the public data bus is used to complete data transmission between the program storage module or data storage module and the CPU.